1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a plurality of memory cells including capacitors, and a method of controlling the same. In particular, the present invention relates to a semiconductor integrated circuit for automatically performing refresh operations to the memory cells and a method of controlling the same.
2. Description of the Related Art
In general, the semiconductor integrated circuits known as having a plurality of memory cells including capacitors include dynamic random access memories (DRAMs). DRAMs are suited for higher integration since their memory cells can be made in smaller configurations. The DRAMs, however, require refresh operations in order to retain data stored in the memory cells.
Meanwhile, the semiconductor integrated circuits known as aimed at both the usability of static RAMs (SRAMs) and the high integration of DRAMs include pseudo SRAMs (PSRAMs) and virtual SRAMs. PSRAMs and virtual SRAMs comprise controlling circuits for refresh operation and memory cores similar to those of DRAMs.
Pseudo SRAMs receive a refresh signal from the exterior, generate refresh addresses within the chips, and perform refresh operations to their memory cells. The pseudo SRAMs are detailed in NIKKEI ELECTRONICS 1986.9.22(no.404) pp.199-217, Nikkei business publications.
Virtual SRAMs incorporate the time required for refresh operations into read cycles and write cycles so that the performances of the refresh operations do not show to the exterior. The virtual SRAMs are detailed in TOSHIBA REVIEW vol.41, no.3, 1986, pp.227-230 (TOSHIBA KK).
Now, in the case where a pseudo SRAM performs refresh operations during intervals between read and write operations, refresh signals must be supplied thereto from the exterior. Therefore, the system using a pseudo SRAM needs to have some controlling circuits such as a refresh timer mounted on its printed-wiring board. Besides, the refresh operations have to be taken into consideration for the circuit design and timing design of the system.
In a virtual SRAM, the cycle times required for read and write operations need to be longer than their actual values by the time required for a refresh operation. This leads to a problem of greatly extended access time.
Accordingly, although both types of the memories are aimed at the usability of SRAMs, their operation cannot be identical to that of SRAMs. Besides, it is not possible not to show their performances of refresh operations completely to the exterior of the chips.